In computer systems, several data sources may be interconnected through a common set of signal lines, known as a bus. Bidirectional buffers with separate drivers and receivers (bus transceivers) are commonly used to interface a data source and/or a data sink to a bus. FIG. 1 is a block diagram representing a data bus which is shared among several data sources and sinks.
In FIG. 1, a CMOS standard cell array 110 and a local memory 112 are coupled via a common local bus 114 to a system bus 118 via a TTL transceiver 116. In this configuration, the memory 112 and gate array 110 may be configured as a state machine which receives input data from and provides output data to the rest of the processing system which is coupled to state machine via the system bus 118.
Bidirectional buffer transceivers, such as the TTL transceiver 116, and similar transceivers (not shown) internal to the gate array 110 and memory 112, allow a two-way transfer of data between a data source/sink and one or more other data source/sinks via the local bus 114. Buffer transceivers are used because they are able to provide the relatively high currents that are desirable to drive multiple data sinks connected to the bus. Bus transceivers typically use two control signals: a direction control signal (not shown) and an output enable signal (not shown). The direction control signal enables the transceiver to place data onto the bus, or to accept data from the bus. The output enable signal determines whether the output terminals of the transceiver are active or disabled.
While active, the transceivers provide the selected output signal which may be in a logic-high or a logic-low state. When the output terminals are disabled, however, the transceivers neither sink current from nor source current to the bus. The voltage level at the output terminals may be high or low, but the transceiver effectively presents an open circuit to the bus. This disabled state is known in the art as the high-impedance state. Since these devices can having three distinct output states (logic-high, logic-low, and high-impedance), they are commonly referred to as TRISTATE.TM. devices.
A bus may be either "pulled-high" or "pulled-low." When a bus is pulled-low, pull-down resistors (not shown) connect the bus to a source (not shown) of reference potential (e.g. ground) which corresponds to a logic-low state. When a bus is pulled-high, pull-up resistors (not shown) are connected between the bus and a source (not shown) of operational potential having a value which corresponds to a logic-high state. Output terminals which are coupled to a bus which is pulled-high and which were in a logic-high state prior to becoming disabled remain in a logic-high state. Output terminals which were in a logic-low state prior to becoming disabled slowly rise to a higher level at a rate determined by the RC time constant of the bus line. The resistance of the pull-up resistors and the reactance of the printed circuit lines that constitute the bus are the main factors that determine this time constant.
Only one data source may assert a signal onto the data bus during a bus cycle. Tristate contention occurs whenever two or more output drivers are enabled to place signals onto the bus simultaneously. This can happen if, for example, there is a delay in disabling one data source so that it remains enabled while another data source is becoming enabled. On a bus with multiple sources, an overlap of this type may cause repeated current spikes when overlapping sources have complementary logic states. These current spikes may significantly shorten the expected lifetime of components used in the system.
FIG. 2 is a simplified block diagram of a prior art system in which several TTL transceiver interfaces provide data individually to several I/O subsystems. System bus 118, known as IBUS in this embodiment, is coupled to supply data to and receive data from several I/O subsystems. In this embodiment of the invention, each I/O subsystem appears to the bus 118 as a CMOS gate array (210, 212 or 214) and a local memory (220, 222 or 224). Data from system bus 118 is distributed to the local busses through each set of transceivers 202, 204 and 206. CMOS gate arrays 210, 212 and 214, and local memories 220, 222 and 224, each may provide data to and receive data from their respective local busses. Thus, it is desirable to prevent simultaneous access to each of the local busses to prevent Tristate contention.
One way in which simultaneous access may be prevented is to inhibit one of the sources to each of the local busses immediately prior to a bus access interval. In the circuitry shown in FIGS. 2 and 3, all of the TTL transceivers 202, 204 and 206 are disabled immediately prior to a bus access interval for the IBUS 118.
FIG. 3 is a logic schematic diagram of the circuitry used to disable each of the TTL transceivers 202, 204 and 206 in the prior art system. In this system, a Tristate disable pulse generator circuit 250 is located on a remote clock generator card. Output disable pulse signals are generated using a 32 Megahertz system clock signal, SCLK, provided by a source 252. In this embodiment of the invention, the source 252 may be, for example, a crystal controlled oscillator (not shown) combined with wave shaping circuitry (not shown) to produce a 32 MHz clock signal having approximately a 50% duty cycle. A 16 Megahertz CMOS clock signal is also provided by source 254. The CMOS clock signal may be obtained, for example, by dividing the signal SCLK in frequency by a factor of two. ECL and TTL delay lines 256, 258, 260, 262 and 264 and logic gates 261, 263 and 266 are used to construct respective active high pulses of the desired shape. The resulting pulse signals are converted from ECL to TTL levels and transmitted from the clock generator card by the drivers 266. It should be noted that although block 253, block 259, and gates 270, 272, 274, 276, 278 and 280 are shown in FIG. 3, a discussion detailing their functions is unwarranted.
Each of the six signals TRISTATE PULSE 1 through TRISTATE PULSE 6 is transmitted over a relatively long cable to reach the respective TTL transceivers (e.g. 202, 204 and 206) which are coupled to the local busses. The loads are distributed as equally as possible over the ECL-to-TTL translator driver devices 266 and are coupled to the respective transceivers via equally long lines to minimize any skew that may exist between the pulse signals.
In this configuration, each TTL transceiver on the local bus receives a 16 nanosecond TRISTATE PULSE which disables the transceiver output ports just prior to the next cycle of a 16 Megahertz local bus access clock signal. In response to the disable pulse, each TTL transceiver forces its output signals to the high impedance state before the next bus cycle begins.
During the next bus cycle, one of the transceivers 202 through 206 may be conditioned to provide data from the IBUS 118 to its associated local bus while one or both of the transceivers internal to the CMOS gate array and the local memory are conditioned to accept data from the local bus.
As an example of how an attempted simultaneous access may occur, consider a sequence of events in which, immediately prior to a bus access period, local memory 220 has been providing data to the CMOS gate array 210 and then, during the bus access period, the TTL transceiver 202 is conditioned to provide data from the bus 118 to the gate array 210. In this sequence of events there may be an overlap in time when the drivers of the TTL transceiver 202 are enabled before the drivers internal to the memory 220 can be disabled. This overlap is dependent upon such factors as the speed of individual drivers and the timing characteristics of the logic in the disable path. In the prior art system described above, a maximum contention time of 5.74 nanoseconds exists when a slow CMOS driver, responding to a slow disable logic signal, continues to drive the bus from a previous cycle while a fast TTL transceiver, responding to a fast enable signal begins to drive the bus on the next cycle. Such contention, repeated millions of times per second, can stress the integrated circuits to the point of failure.
Furthermore, systems which utilize CMOS gate arrays as data sources may exhibit relatively large variations in timing characteristics from among several otherwise identical integrated circuits. Variations in performance characteristics of up to 300 percent are not uncommon among circuits from a given CMOS family. Thus, it may be desirable to employ adjustable delay line circuits to adjust the timing of the respective Tristate disable pulses to compensate for different timing characteristics of individual CMOS gate arrays. These delay elements, however, tend to increase the cost of the system.
Alternatively, this problem may be addressed by defining the bus clock cycle to include a dead cycle of the system clock signal between successive cycles in which a transceiver is allowed to provide data to the bus. Slowly responding transceivers could overlap into this dead cycle without interfering with the activation of the another transceiver during the next bus cycle. This solution is undesirable, however, since it degrades system performance by reducing the data bandwidth of the bus.